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CS4811
Fixed Function Multi-Effects Audio Processor
Features
l Audio
Description
The CS4811 is a complete audio effects processing system on a chip. This device integrates a proprietary 24bit audio processing engine, large on-chip RAM memories, and a high performance 24-bit audio codec. A serial control port allows the device to boot firmware from a compact and low cost SPI or I2C serial EEPROM. Other features such as single +5 V operation simplify system design. There are two different firmware codes available; one for guitar effects and one for audio mixers. The guitar effects firmware provides a host of electric guitar effects including spring reverb, delay, chorus, flange and tremolo. The mixer effects firmware provides a suite of effects such as digital reverb, delay and chorus which are suitable for use in audio mixers, karaoke and acoustic instrument amplifiers. The CDB4811GTR and CDB4811MXR evaluation boards allow easy evaluation of the CS4811 device and the associated firmware. ORDERING INFO CS4811-KM CDB4811GTR-01 CDB4811MXR-01 -10 to +70C 100-pin MQFP Guitar Effects Evaluation Board Mixer Effects Evaluation Board
Processor for embedded reverb/effects applications
- Proprietary 24-bit Audio Processing Engine - On-chip RAM (No external RAM required) - On-chip 24-bit ADC with 100 dB Dyn. Range - On-chip 24-bit DAC with 100 dB Dyn. Range - Automatically boots firmware from external serial EEPROM Firmware for the CS4811 is provided by Cirrus Logic.
l Firmware available for Guitar Effects or Mixer
Effects applications l Single +5 V Supply l 100-pin Metric Quad Flat Pack (MQFP)
I
SPI/I2C
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
RST
XTO XTI
CLOCK MANAGER
SERIAL CONTROL PORT (SPI or I2C)
ANALOG LPF AND OUTPUT STAGE
AOUT+
DIGITAL HPF
24-BIT AUDIO PROCESSING ENGINE
DIGITAL FILTER
DAC
AIN+ AINADC
AOUT-
RAM
VOLTAGE REFERENCE
CMOUT CMFILT+ CMFILT-
OVL
PIO0 PIO1 PIO2 PIO3
Advance Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2000 (All Rights Reserved)
SEP `00 DS486PP2 1
CS4811
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4 ADC CHARACTERISTICS ....................................................................................................... 4 DAC CHARACTERISTICS ....................................................................................................... 5 SWITCHING CHARACTERISTICS .......................................................................................... 6 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MASTER.................................. 7 SWITCHING CHARACTERISTICS - CONTROL PORT - I2C MASTER .................................. 8 RECOMMENDED OPERATING CONDITIONS ....................................................................... 9 DIGITAL CHARACTERISTICS ................................................................................................. 9 SWITCHING CHARACTERISTICS - PROGRAMMABLE I/O................................................... 9 2. TYPICAL CONNECTION DIAGRAMS ................................................................................... 10 3. FUNCTIONAL DESCRIPTION ............................................................................................... 12 3.1 Overview .......................................................................................................................... 12 3.2 Analog Inputs ................................................................................................................... 12 3.2.1 Line Level Inputs ................................................................................................. 12 3.2.2 Digital High Pass Filter ........................................................................................ 12 3.3 Analog Outputs ................................................................................................................ 13 3.3.1 Line Level Outputs .............................................................................................. 13 3.4 Clock Generation ............................................................................................................. 13 3.4.1 Clock Source ....................................................................................................... 13 3.5 Serial Control Port ............................................................................................................ 14 3.5.1 SPI Bus ............................................................................................................... 14 3.5.1.1 SPI Mode ................................................................................................ 14 3.5.2 I2C Bus ................................................................................................................ 14 3.5.2.1 I2C Mode ................................................................................................ 14 3.6 Resets .............................................................................................................................. 15 4. POWER SUPPLY AND GROUNDING ................................................................................... 16 5. PIN DESCRIPTIONS .............................................................................................................. 17 6. PARAMETER DEFINITIONS .................................................................................................. 21 7. PACKAGE DIMENSIONS ..................................................................................................... 22
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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LIST OF FIGURES
Figure 1. SPI Control Port Timing ............................................................................. 7 Figure 2. I2C Control Port Timing .............................................................................. 8 Figure 3. Typical Connection Diagram, Single-ended Input .................................... 10 Figure 4. Typical Connection Diagram, I2C Mode .................................................. 11 Figure 5. Typical Connection Diagram, SPI Mode .................................................. 11 Figure 6. Optional Line Input Buffer ........................................................................ 12 Figure 7. Butterworth Output Filters ........................................................................ 13 Figure 8. Output Mute Circuit .................................................................................. 13 Figure 9. Control Port Timing, SPI Master Mode Self-Boot ..................................... 14 Figure 10.Control Port Timing, I2C Master Mode Self-Boot ..................................... 15 Figure 11.CS4811 Suggested Layout ...................................................................... 16 Figure 12.Pin Assignments ...................................................................................... 17
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1. CHARACTERISTICS AND SPECIFICATIONS
ADC CHARACTERISTICS (TA = 25 C; VA, VD = + 5 V; -1 dB Full Scale Input Sine wave, 997 Hz; Fs = 48 kHz; XTI = 12.2880 MHz; Measurement Bandwidth is 20 Hz to 20 kHz)
Parameters Symbol Stereo Audio channels (A weighted, Note 4) (unweighted, Note 4) (Note 1,4) (Note 5) (Note 2) THD+N Min 16 93 90 1.9 10 (Note 2) -3dB (Note 3) -0.14dB (Note 3) @ 20 Hz (Note 3) CMRR Typ 100 97 -92 2.0 100 2.3 60 3.7 20 10 0 Max 24 -87 0 2.1 15 Units Bits dB dB dB LSB Vrms ppm/C k pF V dB Hz Hz Degree dB
Analog Input Characteristics
ADC Conversion Dynamic Range Total Harmonic Distortion + Noise Offset Error (with internal high pass filter enabled) Full Scale Input Voltage (Differential) Gain Drift Input Resistance Input Capacitance CMOUT Output Voltage Common Mode Rejection Ratio
High Pass Filter Characteristics
Frequency Response Phase Deviation Passband Ripple Notes: 1. Referenced to typical full-scale differential input voltage (2 Vrms). 2. Bench tested only. 3. Filter characteristics scale with output sample rate. 4. Measured using differential analog input circuit, see Figure 6. 5. Filter response is not tested but is guaranteed by design.
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DAC CHARACTERISTICS (TA = 25 C; VA, VD = + 5 V; Full Scale Output Sine wave, 997 Hz; Fs =
48 kHz; XTI = 12.288 MHz; Measurement Bandwidth is 20 Hz to 20 kHz) Parameters DAC Resolution Dynamic Range Offset Voltage (differential) Offset Voltage (V+/V- relative to CMOUT) Full Scale Output Voltage Gain Drift Out of Band Energy Analog Output Load Resistance Capacitance CCIR-2K (DAC not muted, A weighted) THD+N (Note 6) (Note 6) (Differential) (Note 2) (Fs/2 to 2Fs, Note 2) Total Harmonic Distortion + Noise Symbol Min 16 95 1.9 10 Typ 100 -90 -205 -45/-28 2.0 100 -60 74 200 1 50 Max 24 -85 2.1 100 Units Bits dB dB mV mV Vrms ppm/C dBFS k pF dB mA mA dB
Analog Output Characteristics - Minimum Attenuation, 10 k, 100 pF load; unless otherwise specified.
Analog Loopback Performance
Signal-to-Noise Ratio (CCIR-2K weighted, -20 dB input)
Power Supply
Power Supply Current Power Supply Rejection Operating Power Down (Note 7)
(1 kHz, 10 mVrms,, Note 2)
Notes: 6. Measured with DAC calibration disabled. 7. Measured with XTI clock disabled. Specifications are subject to change without notice.
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SWITCHING CHARACTERISTICS (TA = 25 C; VA, VD = +5 V, outputs loaded with 30 pF)
Parameters ADC & DAC Sample Rate XTI Frequency XTI = 256Fs XTI Duty Cycle XTI =256Fs XTI Jitter Tolerance RST Low Time (Note 9) (Note 8) Symbol Fs Min 30 7.68 40 500 Typ 500 Max 50 12.8 60 Units kHz MHz % ps ns
Notes: 8. Guaranteed by characterization but not tested. 9. On power-up, the CS4811 RST pin should be asserted until the power supplies have reached steady state.
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SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MASTER (TA = 25 C,
VA, VD = 5 V; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30 pF) Parameter Symbol SPI Master (Self-Boot) Mode (SPI/I2C = 0, SCPM/S = 1) fsck CCLK Clock Frequency CCLK Low Time CCLK High Time CCLK Rise Time CCLK Fall Time RST rising to CS falling CS High Time Between Transmissions CS Falling to CCLK Edge CS Falling to CDOUT valid CCLK Falling to CDOUT valid CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CS rising (Note 10) (Note 10) tscl tsch tr2 tf2 tsrs tcsh tcss tdv tpd tdsu tdh tclcs Min 37 5 80 80 40 Typ Fs 1/(2*Fs) 1/(2*Fs) 12 12 42 Max 50 100 Units kHz ns ns ns ns s s s ns ns ns ns ns
Notes: 10. Measured with a 2.2 k pullup resistor to VD.
RST
t srs
CS t css CCLK t r2
CDIN
t scl
t sch
t clcs
t csh
t f2
t dsu t dh CDOUT
t dv
t pd
Figure 1. SPI Control Port Timing
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SWITCHING CHARACTERISTICS - CONTROL PORT - I2C MASTER (TA = 25 C;
VA, VD = 5 V; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30 pF) Parameter Symbol Min 4.7 4.0 13.5 250 0 4.7 Typ Fs 1/(2*Fs) 1/(2*Fs) 22 Max 1.5 1 300 Units kHz s s s s s s ns ns s s ns s
I2C(R)
Master (Self-Boot) Mode (SPI/I2C = 1, SCPM/S = 1) (Note 11) fscl SCL Clock Frequency
Clock Low Time Clock High Time Bus Free Time Between Transmissions tlow thigh tbuf tirs thdst tsust tsud (Note 12) (Note 13) (Note 13) thdd tcldv tr tf tsusp
RST rising to start condition Start Condition Hold Time Setup Time for Repeated Start Condition SDA Setup Time to SCL Rising SDA Hold Time from SCL Falling SCL falling to SDA Output Valid SCL and SDA Rise Time SCL and SDA Fall Time Setup Time for Stop Condition
Notes: 11. Use of the I2C bus interface requires a license from Philips. I2C is a registered trademark of Philips Semiconductors. 12. Data must be held for sufficient time to bridge the worst case fall time of 300 ns for CCLK/SCL. 13. For both SDA transmitting and receiving.
RST t irs Stop SDA t buf
SCL
(output)
Start
t
cldv
Repeated Start
Stop
t hdst
t high
t
hdst
tf
t susp
t
low
t
hdd
t sud
t sust
tr
Figure 2. I2C Control Port Timing
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ABSOLUTE MAXIMUM RATINGS (All voltages with respect to AGND = DGND = 0 V.)
Parameters Power Supplies Input Current Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Digital Analog (Note 14) (Note 15) (Note 15) (Power Applied) Symbol VD VA Min -0.3 -0.3 -0.7 -0.7 -55 -65 Typ Max 6.0 6.0 10.0 (VA)+0.7 (VD)+0.7 +125 +150 Units V V mA V V C C
Notes: 14. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 15. The maximum over or under voltage is limited by the input current. Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. (All voltages with respect to AGND = DGND = Min 4.75 4.75 -10 Typ 5.0 5.0 25 Max 5.25 5.25 70 Units V V C
RECOMMENDED OPERATING CONDITIONS
0 V.) Parameters Power Supplies |VA - VD| < 0.4V Operating Ambient Temperature Digital Analog
Symbol VD VA TA
DIGITAL CHARACTERISTICS (TA = 25 C; VA, VD = 5 V)
Parameters High-level Input Voltage Low-level Input Voltage High-level Output Voltage at I0 = -2.0 mA Low-level Output Voltage at I0 = 2.0 mA High-level Input Voltage Low-level Input Voltage Input Leakage Current Output Leakage Current (except XTI) (except XTI) (except XTO) (except XTO) (XTI) (XTI) (Digital Inputs) (High-Z Digital Outputs) Symbol VIH VIL VOH VOL VIH VIL Min 2.8 -0.3 (VD)-1.0 2.8 Typ Max (VD)+0.3 0.8 0.4 2.3 10 10 Units V V V V V V A A
SWITCHING CHARACTERISTICS - PROGRAMMABLE I/O (TA = 25 C; VA, VD = 5 V
5%; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30 pF) Parameters Output Rise Time Output Fall Time DS486PP2 Symbol trpo tfpo Min Typ 200 200 Max Units ns ns 9
CS4811
2. TYPICAL CONNECTION DIAGRAMS
Ferrite Bead + 1 F
A
0.1 F
A
+ 1 F
D
0.1 F
D
+5 V Supply
+
22 F
150
2.2 nF
A
86
AIN+
12 18 88 VA 1..3
65
43 VD 1..2 AOUT + 7 8 ANALOG FILTER
87 0.1 F
100 F
+
A A
AIN -
AOUT -
39
OVL VD 70, 73
CS4811
To Optional Input and Output Buffers 92 1 F
A A
RES-VD
CMOUT
0.1 F
93
+
CMFILT+
1 F
0.1 F
94
CMFILT-
RES-NC RES-NC RES-NC
9, 10, 14, 15, 16, 17, 20 21, 22, 23, 47, 57, 58, 59 60, 61, 71, 95, 97, 90, 91
A
2.2 K
VD VD 2.2 K 63 62
SCL/CCLK SDA/CDOUT
AD0/CS AD1/CDIN
Serial EEPROM
68 67
RES-DGND 69 Mode/Reset Circuit 72 SPI/I2C RES-DGND RES-DGND RES-DGND 41 Control/ Monitor Circuitry 40 37 35 PIO0 PIO1 PIO2 RES-DGND RES-DGND
32, 36, 38, 48, 96, 82, 83 1, 2, 3, 4, 5, 6 24, 25, 26, 27, 28, 29, 30 31, 33, 49, 50, 51, 52, 53 54, 55, 56, 74, 75, 76, 77 78, 79, 80, 81, 84, 85, 98, 99, 100
D
RST
RESET
PIO3
AGND1..4 DGND1..4 11 13 19 89 42 44 64 66 XTO XTI 46 45 1 M Caps, Xtal, and resistor not needed with external clock input to XTI.
RS = 33 All unused inputs should be tied to ground.
A
D
39 pF 39 pF
D D
Figure 3. Typical Connection Diagram, Single-ended Input
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2.2 K
VD VD 2.2 K CS4811 63
SCL/CCLK
SDA/CDOUT AD0/CS
62
A0 A1 A2
D D
I2C EEPROM
68
67
AD1/CDIN
VD 69 SPI/I2C
Reset Circuit
RESET
72
RST
Figure 4. Typical Connection Diagram, I2C Mode
2.2 K
VD VD 2.2 K CS4811 63 62 SCL/CCLK
SPI EEPROM
SDA/CDOUT
AD0/CS AD1/CDIN
68 67
69
D
SPI/I2C
Reset Circuit
RESET
72
RST
Figure 5. Typical Connection Diagram, SPI Mode
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3. FUNCTIONAL DESCRIPTION 3.1 Overview
The CS4811 is a complete audio subsystem on a chip, integrating a proprietary 24-bit audio processing engine with large on chip RAM memories and a single channel 24-bit audio codec. The delta-sigma ADC includes linear phase digital anti-aliasing filters and only requires a single-pole external passive filter. The sigma-delta DAC includes a switched-capacitor anti-image filter and requires an external 2nd or 3rd order active filter that can be easily integrated into the output differential-to-single-ended converter circuit. The serial control port is designed to accommodate I2C(R) or SPI interfaces for stand-alone operation with an external non-volatile memory. pins allows signals centered around 0 V to be input to the CS4811. Figure 3 shows operation with a single-ended input source. This source may be supplied to either the positive or negative input as long as the unused input is connected to ground through capacitors as shown. When operated with singleended inputs, distortion will increase at input levels higher than -1 dB Full Scale. If better performance is required, a single-ended-to-differential converter, shown in Figure 6, may be used. This circuit provides unity gain, DC blocking on the input and anti-alias filtering. The OVL output pin asserts when the analog input is out-of-range.
3.2.2
Digital High Pass Filter
3.2 3.2.1
Analog Inputs Line Level Inputs
AIN+ and AIN- are the differential line level analog inputs (See Figure 3). These pins are internally biased to the CMOUT voltage of 2.3 V. A DC blocking capacitor placed in series with the input
4.7 k
10 F
In DC coupled systems, a small DC offset may exist between the input circuitry and the A/D converters. The CS4811 includes a high pass filter after the decimator to remove these DC components. The high pass filter response, given in High Pass Filter Characteristics, scales linearly with sample rate. Thus, the -3 dB frequency at a 44.1 kHz sample rate will be equal to 44.1/48 times that at a sample rate of 48 kHz.
10 k
input signal (2 Vrms max)
+ 10 k 10 k +5 V -
150 AIN -
+
2.2 nf
150 AIN +
+ CMOUT
from CS4811
+
Buffered CMOUT
+
10 f 0.1 F
GND
Figure 6. Optional Line Input Buffer 12 DS486PP2
CS4811
3.3 3.3.1 Analog Outputs Line Level Outputs
ommended mute circuit referenced in Figure 7. Activating the mute circuit is recommended on power-up and power-down to avoid the output of undesirable audio signals.
The CS4811 contains on-chip differential buffer amplifiers that produce line level outputs AOUT+ and AOUT-, which are capable of driving 10 k loads. These amplifiers are internally biased to the CMOUT voltage of 2.3 V. The recommended off-chip analog filter is a 2nd order Butterworth with a -3 dB corner at Fs. A third order Butterworth filter with a -3 dB corner at 0.75 Fs can be used if greater out of band noise filtering is desired. These filters can be easily integrated into a differential-to-single-ended converter circuit as shown in the 2-pole and 3-pole Butterworth filters of Figure 7. Figure 8 shows the rec-
3.4
Clock Generation
The master clock to operate the CS4811 may be generated by using the on-chip oscillator with an external crystal or may be input from an external clock source.
3.4.1
Clock Source
The CS4811 requires a 256 Fs master clock to run the internal logic. The two possible clock sources are the on-chip crystal oscillator or an external clock input to the XTI pin. The master clock may be generated directly from the on-chip crystal oscillator circuit. When using the on-chip crystal oscillator, external loading capacitors are required. (see Figure 3) High frequency crystals (>8 MHz) should be parallel resonant, fundamental mode and designed for 20 pF loading. (equivalent to 40 pF to ground on each leg) The master clock may also be generated directly from an external CMOS clock input to the XTI pin.
220 pF 14.0 k 14.0 k AOU T1000 pF 14.0 k AOUT+ 1000 pF
BUFFERED CMOUT
3.24 k
+5 V _ + GND
Example Op-Amps are MC33078
MUTE
Line Out
3.24 k
14.0 k
220 pF
2-Pole Butterworth Filter
1 k
220 pF
14.0k 2.8k 11.0k 2.8k
10 F +
Line Out
+5 V _ + GND
MUTE
VA MMBT3906
Line Out
AOU T2200 pF 2200 pF
MMBT3904 10 k 3.3 k
2.8k 11.0k
2.8k
AOUT+
2200 pF
BUFFERED CMOUT
GND
2200 pF
14.0k
220 pF
10 k
3-Pole Butterworth Filter
From CS4811 PIO
10 k MMBT3906 10 F
Figure 7. Butterworth Output Filters
Figure 8. Output Mute Circuit
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3.5 Serial Control Port
CS4811 then automatically clocks out sequential bytes from the EEPROM until the last byte has been received. These bytes include initialization and configuration data for the device along with the application firmware code. After the last byte is received, the CS4811 deasserts CS and begins program execution. At this point, the serial control port becomes inactive and cannot be accessed.
The serial control port is used for self-booting from an external EEPROM and supports both the SPI bus and the I2C(R) bus interfaces. The desired interface is selected via the SPI/I2C pin, which is sampled during de-assertion of the RST pin.
3.5.1
SPI Bus
The SPI bus interface consists of 4 digital signals, CCLK, CDIN, CDOUT and CS. CCLK, the control port bit clock, is used to clock individual data bits. CDIN, the control data input, is the serial data input line to the CS4811. CDOUT, the control data output, is the output data line from the CS4811. CS, the chip select signal, is asserted to enable an external SPI port. Data is clocked in on the rising edge of CCLK and clocked out on the falling edge.
3.5.2
I2C Bus
The I2C bus interface implemented on the CS4811 consists of 2 digital signals, SCL and SDA. SCL or serial clock, is used to clock individual data bits. SDA or serial data, is a bidirectional data line. Two additional pins, AD1 and AD0, are inputs which determine the 2 lowest order bits of the 7-bit I2C device address and should be tied to ground.
3.5.1.1
SPI Mode
3.5.2.1
I2C Mode
The SPI master mode is designed for read-only operation during self-booting from a serial EEPROM. A typical self-boot sequence with a Xicor X25650 serial EEPROM, or equivalent, is shown in Figure 9. On exit from reset, the CS4811 asserts CS. The 8-bit read instruction (00000011) is sent to the EEPROM followed by a pre-defined 16-bit start address. The
The I2C master mode is designed for read-only operation during self-booting from a serial EEPROM. A typical self-boot sequence with a Microchip X24256 serial EEPROM, or equivalent, is shown in Figure 10. On exit from reset, the CS4811 sends an initial write preamble to the EEPROM which consists of a I2C start condition and the slave ad-
CS
0 1 23 4 56 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
CLK
DATA DATA + n
76 5 4 3 2 10
CDIN
READ COMMAND 16-BIT ADDRESS = 0X0000
0 11 00 00 000
76
5
4
3 2 10
CDOUT
00
0
0
0
MSB
Figure 9. Control Port Timing, SPI Master Mode Self-Boot
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dress byte. The slave address consists of the 4 most significant bits set to 1010, the following 3 bits corresponding to the device select bits, A2, A1 and A0 set to 000 and the last bit (R/W) set to 0. Following this, a 2-byte EEPROM starting address of 0x0000 is sent to the EEPROM. The 2-byte EEPROM starting address uses only the lowest 13 bits and sets the highest 3 bits to zero. To begin reading from the EEPROM, the CS4811 sends another start condition followed by a read preamble. The read preamble is identical to the write preamble except for the state of the R/W bit. The CS4811 then automatically clocks out sequential bytes from the EEPROM until the last byte has been received. These bytes include initialization and configuration data for the device along with the application firmware code. After the last byte, the CS4811 initiates a stop condition and begins program execution. At this point, the serial control port becomes inactive and cannot be accessed.
3.6
Resets
Full chip reset can only be achieved by asserting the RST pin. With RST asserted, the chip enters low power mode during which the control port, CODEC and Audio Processor are reset, all registers are returned to their default values and the DAC outputs are muted. The RST pin should be asserted during power-up until the power supplies have reached steady state. If the supply voltage drops below 4 Volts, the CODEC is reset, the DAC outputs are muted and the Audio Processor automatically executes a soft reset. Upon exit from a CODEC reset, the Audio Processor restarts the application code and the CODEC performs the following procedure: * * The CODEC resynchronizes. The DAC outputs unmute.
0
1
2
3
4
5
6
7
8
9
10
16 17 18 19
25 26 27 28 29 30 31 32 33 34 35 36 37
SCL
CHIP ADDRESS (WRITE) MEMORY ADDRESS
0 0 0 0 0 0 1
CHIP ADDRESS (READ)
0 1 0 A2 A1 A0 1
DATA
7 0
DATA +n
7 0
SDA
START
1
0
1
0
A2 A1 A0 0
ACK
ACK
ACK START
ACK
NO ACK STOP
Figure 10. Control Port Timing, I2C Master Mode Self-Boot
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4. POWER SUPPLY AND GROUNDING
Proper layout and grounding is critical to obtaining optimal audio performance in your system. The most important rule to remember is to not allow currents from digital circuitry to couple into sensitive analog circuitry. This is generally done by using a separate or filtered power supply for the analog circuitry, physically separating the analog and digital components and traces in the pcb layout and using wide traces or planes for ground and power. One misplaced component or trace can severely degrade overall system performance. When using separate supplies, the analog and digital power should be connected via a ferrite bead, positioned closer than 1" to the device (see Figure 11). The CS4811 VA pin should be derived from the quietest power source available. If only one supply is available, use the suggested arrangement in Figure 3. A single solid ground plane is the simplest grounding scheme that works well in many cases. In this case, all analog and digital grounds shown in Figure 3 are tied to the same ground plane. However, if separate analog and digital grounds are used, they should be tied together at one point with the location of this point determined by the circuit layout. By considering where the digital ground currents will return to their supply, the connection point can be chosen to keep those currents from flowing through sensitive analog circuit areas. Decoupling capacitors should be placed as close as possible to the device with the lowest value capacitor closest to the chip. Any power and ground connection vias should be placed near their respective component pins and should be attached directly to the appropriate plane. If traces are used for the power supplies to the CS4811, they should be as wide as possible to maintain low impedance. It is recommended to solder the CS4811 directly to the printed circuit board. Soldering improves performance and enhances reliability. For an example layout, please refer to the CDB4811 data sheet.
> 1/8"
Digital Power Plane
Ferrite Bead
Note that the CS4811 is oriented with its digital pins towards the digital end of the board.
CS4811
Analog Power Plane
Digital Interface
Analog Signals & Components
Figure 11. CS4811 Suggested Layout
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5. PIN DESCRIPTIONS
DGND AD1/CDIN AD0/CS SPI/I2C RES-VD RES-NC RST RES-VD NC NC NC NC NC NC NC NC RES-DGND RES-DGND NC NC AIN+ AINVA AGND RES-NC RES-NC CMOUT CMFILT+ CMFILTRES-NC RES-DGND RES-NC NC NC NC NC NC NC NC NC NC AOUT+ AOUTRES-NC RES-NC AGND VA AGND RES-NC RES-NC
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
CS4811 100-PIN MQFP
VD DGND SCL/CCLK SDA/CDOUT RES-NC RES-NC RES-NC RES-NC RES-NC NC NC NC NC NC NC NC NC RES-DGND RES-NC XTO XTI DGND VD DGND PIO0 PIO1 OVL RES-DGND PIO2 RES-DGND PIO3 RES-DGND NC RES-DGND NC NC NC NC NC NC NC NC RES-NC RES-NC RES-NC RES-NC AGND VA RES-NC RES-NC
Figure 12. Pin Assignments
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CS4811
Power Supply
VA - Analog Power Power: analog supply, +5 V. AGND - Analog Ground Ground: analog ground. VD - Digital Power Power: digital supply, +5 V. DGND - Digital Ground Ground: digital ground.
Analog Input
AIN+/- - Differential Audio Input Inputs: These pins accept differential analog input signals and are biased to the internal reference voltage of approximately 2.3 V. The + and - input signals should be 180 out of phase resulting in a nominal differential input voltage of twice the input pin voltage. A single-ended signal may also be directly applied to either the + or - input with the other input AC coupled to ground through a capacitor. In general, differential input signals provide better performance. However, singled-ended inputs may result in reduced cost. Inputs may be AC or DC coupled. DC coupled input signals must be biased at 2.3 V. Any remaining DC offset is removed by an internal digital HPF. For best performance, a passive anti-aliasing filter is required. The typical connection diagram in Figure 3. shows the recommended single-ended input circuit. Figure 6 shows the recommended differential input circuit. OVL - ADC Overload Indicator Output: This pin is asserted when the ADC is clipping. The pin does not latch and de-asserts when clipping stops.
Analog Output
AOUT+/- - Differential Audio Output Outputs: These pins output differential analog signals which are biased to the internal reference voltage of approximately 2.3 V. The + and - output signals are 180 out of phase resulting in a nominal differential output voltage of twice the output pin voltage. For best performance, an anti-imaging filter is required. Figure 7 shows the recommended second and third order Butterworth differential-to-singleended output buffer circuits.
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CS4811
Voltage Reference
CMOUT - Common Mode Output Output: This pin provides an internally generated reference of 2.3 V to be used for biasing external analog circuitry. The load on CMOUT must be DC only, with an impedance of not less than 50 kilohms. CMFILT+,CMFILT- - Common Mode Filter Connections Inputs: These pins are connections for external filter components required by the internal common mode reference circuit. See the typical connection diagram in Figure 3. for details.
Serial Control Port SPI/I2C - Serial Control Port Format Select
Input: This pin configures the control port for I2C format if tied to VD or SPI format if tied to DGND. SCL/CCLK - Serial Control Port Clock Output: This pin clocks serial control port data into and out of SDA in I2C mode. In SPI mode, it clocks control port data into CDIN and out of CDOUT. AD0/CS - I2C Address Bit 0 / SPI Chip Select Input/Output: In I2C(R) mode, AD0 is an input and must be tied to ground. In SPI mode, CS is an output and is used to select the boot EEPROM. AD1/CDIN - I2C Address Bit 1 / SPI Data Input Input: In I2C(R) mode, AD1 is an input and must be tied to ground. In SPI mode, CDIN is the serial control port data input and is clocked in on the rising edge of CCLK. SDA/CDOUT - I2C Data / SPI Data Output Bidirectional/Output: In I2C(R) mode, SDA is the bidirectional data I/O line. In SPI mode, CDOUT is the serial control port data output and is clocked out on the falling edge of CCLK.
Clock and Crystal
XTI, XTO - Crystal Oscillator Connections (Master Clock) Input, Output: These pins provide connections for an external parallel resonant quartz crystal. Alternately, an external clock source may be applied to XTI. The clock frequency must be 256xFs.
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CS4811
Miscellaneous
PIO0:3 - General Purpose Inputs/Outputs Bidirectional: These pins are general-purpose digital I/O pins. The Default state is input. functionality of these pins after boot-up is determined by the application firmware. RST - Reset Input: This pin causes the device to enter a low power mode and forces all control port and I/O registers to be reset to their default values. The control port can not be accessed when reset is low. NC - No Connect Input: These pins are not internally connected and should be tied to ground for optimal performance. RES-NC - Reserved, No Connect
These pins are reserved and must be left unconnected for normal operation. The
RES-VD - Reserved, Connect to VD
These pins are reserved and must be tied to VD for normal operation.
RES-DGND - Reserved, Connect to DGND
These pins are reserved and must be tied to digital ground for normal operation.
RES-AGND - Reserved, Connect to AGND
These pins are reserved and must be tied to analog ground for normal operation.
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CS4811
6. PARAMETER DEFINITIONS
Dynamic Range The ratio of the full scale RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbFs signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Total Harmonic Distortion + Noise The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth (typically 20 Hz to 20 kHz), including distortion components. Expressed in decibels. ADCs are measured at -1 dBFs as suggested in AES 17-1991 Annex A. Idle Channel Noise / Signal-to-Noise-Ratio The ratio of the RMS analog output level with 1 kHz full scale digital input to the RMS analog output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz bandwidth. Units in decibels. This specification has been standardized by the Audio Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio. Total Harmonic Distortion (THD) THD is the ratio of the test signal amplitude to the RMS sum of all the in-band harmonics of the test signal. Units in decibels. Interchannel Isolation A measure of crosstalk between channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Frequency Response A measure of the amplitude response variation from 20 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Gain Mismatch For the ADCs, the difference in input voltage that generates the full scale code for each channel. For the DACs, the difference in output voltages for each channel with a full scale digital input. Units are in decibels. Gain Error The deviation from the nominal full scale output for a full scale input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error For the ADCs, the deviation in LSB's of the output from mid-scale with the selected input grounded. For the DAC's, the deviation of the output from zero (relative to CMOUT) with mid-scale input code. Units are in volts.
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7. PACKAGE DIMENSIONS
100L MQFP PACKAGE DRAWING
E E1
D D1
1
e
B A A1
L
INCHES MIN NOM --0.010 0.012 0.009 0.012 0.667 0.677 0.547 0.551 0.904 0.91 0.783 0.79 0.022 0.026 0.000 4.00 L 0.029 0.035 * Nominal pin pitch is 0.65 mm = 0.65 BSC DIM A A1 B D D1 E E1 e* Controlling dimension is mm. JEDEC Designation: MS022 ASE/SPIL MILLIMETERS NOM -0.30 0.30 17.20 14.00 23.20 20.0 0.65 4.00 0.88
MAX 0.134 0.014 0.015 0.687 0.555 0.923 0.791 0.030 7.000 0.041
MIN -0.250 0.220 16.950 13.900 22.950 19.900 0.550 0.00 0.73
MAX 3.400 0.350 0.380 17.450 14.100 23.450 20.100 0.750 7.00 1.03
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* Notes *

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